This invention relates to a clock controlling method and a clock control circuit. More particularly, it relates to a clock controlling method and a clock control circuit convenient for generating a clock signal having a multiplied frequency of an external clock and being synchronized with the external clock.
Recently, with an increasing size of circuits that can be integrated on one chip and with an increasing operating frequency, a clock control circuit has come to be used for controlling the phase and frequency of clock inside and outside a chip of a semiconductor integrated circuit including a synchronization circuit operating on a clock signal supplied to the circuit.
As a clock control circuit, a feedback type circuit, such as a PLL (phase locked loop) or a DLL (delay synchronization loop), has so far been used. Of these, the PLL circuit is made up of a phase comparator circuit receiving a reference clock signal as an input, a charge pump for charging and discharging a capacitor to generate a voltage corresponding to a phase difference output from the phase comparator circuit, a loop filter for smoothing a voltage corresponding to the phase difference, a voltage controlled oscillator receiving a voltage output from the loop filter as a control voltage to vary an oscillation frequency responsive to the control voltage, and a frequency divider for frequency dividing an oscillation output signal from the voltage controlled oscillator to provide a frequency divided signal to the phase comparator circuit. The phase comparator circuit compares the phase difference between the reference clock signal and the signal output from the frequency divider to control the oscillation frequency of the voltage controlled oscillator responsive to the result of phase comparison and hence the voltage controlled oscillator is made to output a clock signal which is phase-synchronized with the reference clock signal which is provided to the phase comparator circuit.
As a circuit for frequency multiplying an input clock, a circuit comprised of the combination of a PLL circuit and an interpolator (interior division circuit) is known in the art. See, for example, Publication 1 (ISSC 1993 p.p. 160-161, Mark Horowitz et al., xe2x80x9cPLL Design for 500 MHz Interfacexe2x80x9d). Meanwhile, the interpolator disclosed in this Publication 1 is of an analog circuit configuration made up of a differential circuit receiving two inputs.
As is well-known, the configuration employing a PLL circuit suffers from the problem that phase synchronization is extremely time-consuming, and that there persists phase jitter ascribable to a feedback loop and marked phase shifting is produced in case the locked state is disengaged due to such jitter.
As a non-feedback type frequency multiplied clock generating circuit, not employing the feedback system, such as PLL, the present inventors have already proposed a construction in e.g., JP Patent Application No. 11-004145, as shown in FIGS. 12 to 15 hereof. Referring to FIG. 12, this multiplier circuit includes a frequency divider 2 for dividing the frequency of the input clock 1 to generate multi-phase clocks 3, a multi-phase clock multiplier circuit 5, which receives output 3 from the frequency divider 2, as an input, a period detection circuit 6, made up of a ring oscillator of a fixed number of stages and a counter for counting the number of times of oscillations of the ring oscillator during one clock period of the input clock 1 to detect the period of the clock 1 to output a control signal 7, and a clock synthesis circuit 8 for synthesizing the output signal of the multi-phase clock multiplier circuit 5 to generate a frequency multiplied clock signal. The multi-phase clock multiplier circuit 5 includes plural timing difference division circuits 4a for outputting signals corresponding to the interior division of the timing difference (phase difference) of two inputs and plural multiplexing circuits 4b for multiplexing output signals of two of the timing difference division circuits.
The plural timing difference division circuits 4a are comprised of plural timing difference division circuits which receives clock signals of the same phase as inputs, and plural timing difference division circuits which receives two neighboring clock signals. The period detection circuit 6 outputs a control signal 7 to adjust the load capacitance of the timing difference division circuits 4a in the multi-phase clock multiplier circuit 5 to control the clock period.
FIG. 13 shows, as an example of the clock multiplier circuit, a specified illustrative structure of a four-phase clock multiplier circuit for generating four-phase clocks. Referring to FIG. 13, the four-phase clock multiplier circuit includes a xc2xc frequency divider circuit 201 for frequency dividing an input clock 205 by four to output four-phase clocks Q1 to Q4, a n-stage cascaded connection of four-phase clock multiplier circuits 2021 to 202n, a clock synthesis circuit 203 and a period detection circuit 204. The last stage four-phase clock multiplier circuit 202n outputs 2n-multiplied four-phase clocks Qn1 to Qn4, which are synthesized in the clock synthesis circuit 203 so as to be output as a multiplied clock signal 207. Meanwhile, the number of stage n of the four-phase clock multiplier circuits is arbitrary.
The xc2xc frequency divider 201 frequency divides the input clock 205 by four to generate four-phase clocks Q1 to Q4 which are then multiplied by the four-phase clock multiplier circuit 2021 to generate four-phase clocks Q11 to Q14. In similar manner, 2n-tupled four-phase clocks Qn1 to Qn4 are produced from the four-phase clock multiplier circuit 202n.
The period detection circuit 204 is made up of a ring oscillator having a fixed number of stages and a counter. During the periods of the clocks 205, the number of times of oscillations of the ring oscillator is counted by the counter to output control signals 206 depending on the number of counts to adjust the load in the four-phase clock multiplier circuit 202. This period detection circuit 204 resolves fluctuations in device characteristics during the clock period operation.
The operation of the four-phase clock multiplier circuit 202 is explained. The four-phase clocks are converted into eight phase clocks by the four-phase lock multiplier circuit 202 of FIG. 13 and converted back to four-phase clocks to effect multiplication continuously, as now explained in detail.
FIG. 14 shows an illustrative structure of the four-phase clock multiplier circuit 202n shown in FIG. 13. Meanwhile, the four-phase clock multiplier circuits 2021 to 202n are of the same structure.
Referring to FIG. 14a, this four-phase clock multiplier circuit 202n is made up of eight sets of timing difference division circuits 208 to 215, eight sets of pulse width correction circuits 216 to 223 and four sets of multiplexer circuits 224 to 227. FIG. 14b shows the structure of a pulse width correction circuit comprised of a NAND circuit receiving signals corresponding to the second input T23 inverted by an inverter INV and the first input T21, as inputs. FIG. 14c shows the structure of a multiplier circuit comprised of a two-input AND circuit.
FIG. 15 shows a signal waveform diagram for illustrating the timing operation of the four-phase clock multiplier circuit 202 shown in FIG. 14. The rising of the clock T21 is determined by a delay corresponding to the internal delay of the timing difference division circuit 208 as from the rising of the clock Q(nxe2x88x921)1, the rising of the clock T22 is determined by timing division by a timing difference division circuit 209 of the timing difference between the rise timing of the clock Q(nxe2x88x921)1 and the rise of the clock Q(nxe2x88x921)2 and by the delay corresponding to the internal delay, and the rise timing of the clock T23 is determined by the timing division by a timing difference division circuit 210 of the timing difference between the rise timing of the clock Q(nxe2x88x921)1 and the rise timing of the clock Q(nxe2x88x921)2 and by the delay corresponding to the internal delay. In similar manner, the rising of the clock T26 is determined by the timing division by a timing difference division circuit 213 of the timing difference between the rise timing of the clock Q(nxe2x88x921)3 and the rise timing of the clock Q(nxe2x88x921)4 and by the delay corresponding to the internal delay, the rising of the clock T27 is determined by the delay corresponding to the internal delay in the timing difference division circuit 214 of the rise timing of the clock Q(nxe2x88x921)4 and the rising of the clock T28 is determined by the timing division by a timing difference division circuit 215 of the timing difference between the rise timing of the clock Q(nxe2x88x921)4 and the rise timing of the clock Q(nxe2x88x921)1 and by the delay corresponding to the internal delay.
Clocks T21, T23 output by the timing difference division circuits 208, 210 are input to the pulse width correction circuit 216. The pulse width correction circuit 216 outputs a pulse P21 having a falling edge determined by the clock T21 and a rising edge determined by the clock T23. By a similar sequence of operations, pulses P22 to P28 are generated. The clocks P21 to P28 are 25-duty % eight-phase pulses, each phase being spaced by 45xc2x0 from one another. The clock P25, the phase of which being shifted by 180xc2x0 from that of the clock T21, is multiplexed by a multiplexer circuit 224 and output as a duty-25% clock Qn1. In similar manner, clocks Qn2 to Qn4 are generated. The clocks Qn1 to Qn4 become duty-50% four-phase pulses each phase being spaced by 90xc2x0 from one another which are frequency multiplied by two in the course of generating clocks Qn1 to Qn4 from the clocks Q(nxe2x88x921)1 to Q(nxe2x88x921)4.
FIG. 16 shows an illustrative structure of timing difference division circuits 208, 209 shown in FIG. 14. The same signal is input to two inputs IN1 and IN2 of the timing difference division circuit 208, whereas two neighboring signals are input to the two inputs IN1 and IN2 of the timing difference division circuit 209. That is, the same input Q(nxe2x88x921) is fed to the input terminals IN1, IN2 of the timing difference division circuit 208, whereas inputs Q(nxe2x88x921)1 and Q(nxe2x88x921)2 are fed to the input terminals IN1, IN2 of the timing difference division circuit 209. The timing difference division circuit includes a p-channel MOS transistor MP01, having its source and drain connected to the power supply VDD and to an internal node N1, respectively, an OR gate OR1 which receives the input signals IN1, IN2 and has its output terminal connected to the gate of the p-channel MOS transistor MP01, and n-channel MOS transistors MN01, MN02, having drains connected to the internal node N1 and sources connected via a constant current source 10 to the ground, while having gates fed with the input signals IN1, IN2 respectively. The internal node N1 is connected to an input terminal of an inverter INV01. A series connection of the n-channel MOS transistor MN11 and a capacitor CAP11, a series connection of the n-channel MOS transistor MN12 and a capacitor CAP12, . . . and a series connection of the n-channel MOS transistor MN15 and a capacitor CAP15 are connected in parallel across the internal node N1 and the ground. The gates of the n-channel MOS transistors MN11, MN12, MN13, MN14 and MN15 are fed with a 5-bit control signal 206 from a period detection circuit 204 to turn the transistors on or off. The gate widths of the n-channel MOS transistors MN11, MN12, MN13, MN14 and MN15 are and the capacitances CAP11, CAP12, CAP13, CAP14 and CAP15 are of the size ratio of, for example, 16:8:4:2:1, so that the load connected to the common node is adjusted in 32 stages, based on a control signal 206 output from the period detection circuit 204, to set the clock period.
As for the timing difference division circuit 208, the charge at the node N1 is extracted through the two n-channel MOS transistors MN11 and MN12 by the rising edge of the clock Q(nxe2x88x921)1, commonly fed to the two inputs IN1, IN2. When the voltage level of the node N1 reaches the threshold voltage of the inverter INV01, the clock T21, output by the node N1, rises. If the charge stored at the node N1, that need to be extracted in order for the node N1 to reach the threshold voltage of the inverter INV01 is CV, where C and V denote the capacitance and the voltage, respectively, and the discharge current by the n-channel MOS transistor is I, the charge CV is discharged at a constant current of 2I as from the rise edge of the clock Q(nxe2x88x921)1. So, the time CV/2I represents the timing difference from the rising edge of the clock Q(nxe2x88x921)1 to the rising edge of the clock T21 (propagation delay time).
When the clock Q(nxe2x88x921)1 is at a low level, the p-channel MOS transistor MP01 is turned on, the node N1 is charged to a high level and the output clock T21 of the inverter INV01 goes down to a low level.
As for the timing difference division circuit209, charge at node N1 is extracted during the time after time tCKn (=multi-phase clock period) as from the rising edge of the clock Q(nxe2x88x921)1. When the potential of the node N1 has reached the threshold voltage of the inverter INV01, as from the rising edge of the clock Q(nxe2x88x921)2 after time tCKn, the clock T22 rises. If the electric charge of the node N1 is CV and the discharge current of the NMOS transistor is I, the charge CV in the capacitor C is discharged as from the rising of the clock Q(nxe2x88x921)1 during the time tCKn with the constant current I, while being discharged during the remaining period with the constant current 2I. As a result, the time
tCKn+(CVxe2x88x92tCKnxc3x97I)/2I=CV/2I+tCKn/2xe2x80x83xe2x80x83(1) 
represents the timing difference as from the rising edge of the clock Q(nxe2x88x921)1 until the rising edge of the clock T22.
That is, the timing difference between the rising edge of the clock T22 and the rising edge of the clock T21 is tCKn/2.
When the clocks Q(nxe2x88x921)1 and Q(nxe2x88x921)2 both go at a low level, and the node N1 is charged through the p-channel MOS transistor MP01 from the power supply to a high level, the clock T22 falls. The same applies for the clocks T22 to T28, such that the timing difference of the clocks T21 to T28 is equal to tCKn/2.
The pulse width correction circuits 216 to 223 generate duty-25% eight-phase pulses P21 to P28, which are phase shifted by 45xc2x0 from one another (see FIG. 14).
The multiplexing circuits 224 to 227 generate duty 50% four-phase pulses Qn1 to Qn4, each phase being spaced by 90xc2x0 from one another.
The timing difference division circuit of FIG. 16 is suitably changed depending on the application used. For example, it is also possible to provide an output of a NAND circuit which receives the first and second input signals IN1, IN2, to the gate of the p-channel MOS transistor MP01 and to input the first input signal IN1 and the second input signal IN2, inverted by the inverter, to the gates of the n-channel MOS transistors MNO1 and MNO2. In this case, when the first and second input signals IN1, IN2 are at a high level, the p-channel MOS transistor MP01 is turned on to charge the internal node N1, with the output signal of the inverter INV01 going to a low level. When one or both of the first and second input signals IN1 and IN2 are at a low level, the p-channel MOS transistor MP01 is turned off, and one or both of the p-channel MOS transistors MNO1 and MNO2 is turned on to discharge the internal node N1. When the voltage of the internal node N1 falls to below the threshold value of the inverter INV01, the output signal of the inverter INV01 rises to a high level.
In the above-described clock control circuit, employing the PLL, in which an oscillation output signal from the voltage controlled oscillator (VCO) and the input signal (reference signal) are controlled so as to match in phases to each other, a lock process is time consuming, and it is difficult to output a signal synchronized with the oncoming input clock immediately from the clock cycle next following the oncoming input clock in case of the PLL being in an unlocked state or in case of no input clock(reference signal) being provided to the PLL from the perspective of the circuit structure.
In the clock multiplier circuit, employing the conventional timing difference division circuit, a timing signal corresponding to the interior division of the phase difference of two input signals can be output with high precision, however, should variations such as those in the manufacturing process or power supply state be produced, these variations are presented as variations in the delay time of the timing difference division circuit. For example, there are occasions where variations in the threshold voltage V, constant current I (drain current of the n-channel MOS transistor) or the capacitance value C in CV/2I in the above equation (1) affect the delay time of the timing difference division circuit, and as a result, jitters may be produced in output signal in the clock multiplier circuit made up of plural stages of parallel connections of the timing difference division circuits.
In the above-described clock multiplier circuit employing the timing difference division circuit (see FIG. 12) and employing no feedback circuit as a PLL circuit or the like, it is difficult to generate multiplexed signals phase-synchronized with the external clock received.
In a configuration not employing a feedback circuit, such as PLL circuit, it is difficult to generate from an input external clock a multiplied signal of equal time intervals by dividing one period of the external clock due to such as jitter of the output signal of the timing difference division circuit.
It is therefore an object of the present invention to provide a novel clock control circuit for generating multi-phase clocks phase-synchronized to an external clock and a frequency multiplied clock signal without recourse to a feedback system, a semiconductor integrated circuit device having the clock control circuit, and a clock controlling method.
It is another object of the present invention to provide a novel clock control circuit for generating multi-phase clocks having equal clock intervals and a frequency multiplied clock signal by a simplified structure without recourse to a feedback system, a semiconductor integrated circuit device having the clock control circuit, and a clock controlling method.
For accomplishing the above object, a clock control circuit in accordance with one aspect of the present invention, comprises a delay circuit sequence including a plurality of cascaded stages of delay circuit units, each made up of a first circuit receiving an input signal to output said input signal with a first delay time and a second circuit receiving an output signal from said first circuit to output said signal with a second delay time; a phase difference detection circuit receiving an input clock fed to said delay circuit sequence and an output clock output from said delay circuit sequence to detect a time difference between a clock period of said input clock and a delay time of said delay circuit sequence as a phase difference of said received two clocks; and a plurality of third circuits, each receiving an output signal of said first circuit of each of said delay circuit units to delay and output transition edge of said output signal of said first circuit with respective different delay time, in accordance with a stage number of said delay circuit unit to which belongs said first circuit in said delay circuit sequence, in terms of time obtained on equally dividing said phase difference by the stage number of said delay circuit units in said delay circuit sequence, as a unit; wherein said third circuits output a plurality of output signals which make transition at a time interval corresponding to equal division of the clock period of said input clock by the number of said delay circuit units in said delay circuit sequence.
In accordance with one aspect of the present invention, the third circuit includes a circuit controlling charging and discharging of a capacitor; and a circuit outputting, as said output signal of said third circuit, a logic value corresponding to the magnitude relation between a terminal voltage of said capacitor and a threshold value; and wherein said capacitor is charged or discharged during the time corresponding to said phase difference, said capacitor is again discharged or charged following said discharging or charging during the time period corresponding to the phase difference, responsive to transition of an output signal of said first circuit of the delay circuit unit associated with said third circuit; and a rise or fall transition edge of an output signal of said first circuit of said delay circuit unit associated with said third circuit is output with a delay equal to time corresponding to said second delay time less a delay time corresponding to a phase obtained on multiplying a phase obtained by equally dividing the phase difference by a number equal to the number of delay circuit units with a value indicating the stage number in said delay circuit sequence of said delay circuit unit corresponding to said third circuit.
According to the present invention, there is provided a synthesis circuit for generating and outputting a frequency multiplied clock signal of a period obtained on equal division of a clock period of the input clock based on the input signal and on output signals of the third circuits.
In accordance with one aspect of the present invention, there are provided a plural number of cascaded stages of delay circuit units each made up of a first delay circuit with a first delay time t1 and a second delay circuit for delaying and outputting the rise or fall transition edge of an output signal of the first delay circuit with a second delay time t2, with the delay circuit sequence being fed from the last stage delay circuit unit of the delay circuit sequence with input clock with a clock period tCK, and a phase difference detection circuit for detecting, from output clocks output by the last stage delay controlled unit of the delay circuit sequence and an input clock input to the delay circuit sequence and from the input clock input to the delay circuit sequence, the phase difference T corresponding to the time difference between the delay time of the delay circuit sequence and the period tCK of the input clock (T=Nxc3x97(t1+t2xe2x88x92tCK).
There are also provided (Nxe2x88x921) third delay circuits, each fed with an output signal of a first delay circuit of from stage number 1 to stage number (Nxe2x88x921) delay circuit unit, with a third delay circuit of a number n third delay circuit, where n is a positive integer of from 1 to Nxe2x88x921, delaying the transition edge of an output signal of the first delay circuit of a corresponding stage number n delay circuit unit, based on the phase difference T as detected by the phase difference detection circuit, by time t2xe2x88x92nxc3x97T/N corresponding to second delay time t2 less a delay time nxc3x97T/N corresponding in turn to the phase T/N obtained on equally dividing the phase difference T by the number N of the delay circuit units multiplied by the number of states n in the delay circuit sequence of delay circuit units corresponding to the third delay circuit and outputting the delayed signal.
The number n third delay circuit, where n is an integer from 1 to Nxe2x88x921, outputs a signal which goes high or low at a timing delayed from a start time point of a clock cycle of the input clock by time nxc3x97(t1+t2xe2x88x92T/N)=nxc3x97tCK/N.
There is also provided a synthesis circuit for generating a frequency multiplied clock signal of a clock period obtained on equally dividing the clock period tCK of input clock from the input signal and from number 1 to number (Nxe2x88x921) third delay circuits.
The present invention also provides a clock control circuit including a delay circuit sequence comprised of a plural number (N) of cascaded stages of first delay circuits each with delay time t1, with the delay circuit sequence being fed with input clock of a period tCK from a stage number 1 first delay circuit, a phase difference detection circuit for detecting the phase difference T (T=tCK-Nxc3x97t1) corresponding to the delay time of the delay circuit sequence and the clock period tCK of input clock, from output clocks from the last stage first delay circuit of the delay circuit sequence and input clock input to the delay circuit sequence, and N second delay circuits fed respectively with output signals of number 1 to number N first delay circuits.
The number n second delay circuit, n being a positive integer from 1 to N, delays a transition edge of an output signal of the corresponding stage number n first delay circuit by a time prescribed by a delay time proper to the second delay circuit tpd less (Nxe2x88x92n)xc3x97T/N where T/N corresponds to the phase difference T divided equally by the total number of first delay circuits and N-n corresponds to the difference between N and the stages n of first delay circuits in delay circuit sequence.
The number n second delay circuit, n being a positive integer from 1 to N, outputs signals making rise or fall transition with a timing delayed by
nxc3x97t1+tpdxe2x88x92(1xe2x88x92n/N)xc3x97T 
as from the start time point of the clock cycle of input clock, with multi-phase clocks with a time interval of t1+T/N being generated from an output signal of each of the number 1 to number N second delay circuits.
A clock controlling method in accordance with one aspect of the present invention includes following steps,
step1: entering an input clock to a delay circuit sequence including a plurality of cascaded stages of delay circuit units each made up of a first circuit for outputting an input signal with a first delay time and a second circuit for outputting an output signal of said first circuit with a second delay time,
step2: detecting, by a phase difference detection circuit, a phase difference between a clock pulse of the clock cycle next to the input clock fed to said delay circuit sequence and a clock pulse output from the last state delay circuit unit of the delay circuit sequence, that is a difference between the delay time of the delay circuit sequence and the clock period of input clock,
step3: outputting, from a plurality of third circuits which receives output signals of the first circuits of said plural delay circuit units, transition edges of the output signals of said first circuits with respective different delay time, in accordance with a stage number of said delay circuit unit to which belongs said first circuit in said delay circuit sequence, in terms of time obtained on equally dividing said phase difference by the number of said delay circuit units in said delay circuit sequence, as a unit; wherein said third circuits outputting a plurality of output signals which make transition at a time interval corresponding to equal division of the clock period of said input clock with the number of said delay circuit units in said delay circuit sequence.
The above objets may also be accomplished by another aspect of the invention. In accordance with another aspect of the present invention, a clock control circuit includes a first delay circuit sequence including plural cascaded stages of delay circuits,
a second delay circuit sequence including plural cascaded stages of delay circuits, an input clock entered to the stage 1 delay circuit of the first delay circuit sequence being output from the last stage delay circuit of the first delay circuit sequence after propagation through the first delay circuit sequence to be entered to the stage 1 delay circuit of second delay circuit sequence for propagation through the second delay circuit sequence. A plural number of interior division circuits are mounted in juxtaposition to one another in association with respective stages of the delay circuits of the first and second delay circuit sequences for outputting output signals with a delay time prescribed by the time corresponding to division of the phase difference between two input signals with a preset interior division ratio. The number 1 interior division circuit of juxtaposed plural interior division circuits is fed with an input clock output by the first delay circuit sequence and fed to the stage number 1 delay controlled of the second delay circuit sequence and the next cycle input clock.
The interior division ratio of plural interior division circuits is set such as to increase the respective delay time every preset unit T/N, with the phase different between output signals of two neighboring interior division circuits being tCK/N, with the phase difference between the output signal of the number 1 interior division circuit and the number N interior division circuit being the input clock period or tCK.
A clock control circuit includes a first delay circuit sequence including 2N cascaded stages of first delay circuit sequences, with a non-inverting phase clock being input at a stage number 1 delay circuit of first delay circuit sequence for propagation through the first delay circuit sequence, where N is an integer not less than 1, a second delay circuit sequence including 2N cascaded stages of first delay circuit sequences, with an inverting-phase clock being input at a stage number 1 delay circuit of second delay circuit sequence for propagation through second delay circuit sequence, where N is an integer not less than 1, and first and second groups of interior division circuits, each group including (N+1) interior division circuits for outputting an output signal of a delay time prescribed by the time obtained on dividing the phase difference of two input signals with a preset interior division ratio. The interior division ratio of (N+1) interior division circuits is set to respective different values in each group.
The number 1 interior division circuit of the first group of the interior division circuits is fed with an output signal of the stage number N delay circuit of the second delay circuit sequence and with a forward phase clock of the next cycle.
The number i interior division circuit of the first group of the interior division circuits, i being a number from 2 to N+1, is fed with an output signal of the number (N+1xe2x88x921) delay circuit of the second delay circuit sequence and with an output signal of the delay circuit of the (ixe2x88x921) stage number delay circuit of the first delay circuit sequence fed with forward phase clocks of the next cycle. The number 1 to number N interior division circuits output multi-phase clocks of a phase difference corresponding to N equal division of the input clock period. As will become clear from the following explanation, the above objects may similarly be achieved by the subject matter of the invention as defined on the respective claims.
A clock controlling method in accordance with another aspect of the present invention includes following steps,
step1: connecting 2N cascaded stages of delay circuits, N being an integer not less than 1, inputting input clock to a stage number 1 delay circuit of a delay circuit sequence,
step2: at least N interior division circuits for outputting an output signal of a delay time prescribed by time obtained on dividing a phase difference of two input signals by a predetermined interior division ratio, with the interior division ratio of said plural interior division circuits being set to respective different values,
step3: the interior division circuit receiving an output signal of the stage number N delay circuit and with the input clock of the next cycle, and outputting an output signal of a delay time prescribed by the time obtained on dividing the phase difference of two input signals with a predetermined interior division ratio;
the interior division circuit fed with an output signal of the stage number (N+i) delay circuit, i being an integer from 1 to Nxe2x88x921, and with an output signal of the stage number i of the delay circuit of the next cycle input clock, outputting an output signal of a delay time prescribed by time obtained on dividing the phase difference of the two input signals by a preset interior division ratio; and
step4:generating multi-phase clocks of a phase difference corresponding to N equal division of the input clock period through N of said interior division circuits.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out this invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.